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Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert

This commit is contained in:
Dolu1990 2022-11-28 16:30:47 +01:00
parent eafeb5fe49
commit fb084327da
1 changed files with 4 additions and 1 deletions
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5
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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@ -143,7 +143,10 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
softwareInterrupt load plugin.softwareInterrupt softwareInterrupt load plugin.softwareInterrupt
if (plugin.config.supervisorGen) externalSupervisorInterrupt load plugin.externalInterruptS if (plugin.config.supervisorGen) externalSupervisorInterrupt load plugin.externalInterruptS
withDebug.get match { withDebug.get match {
case DEBUG_RISCV => debugRiscv <> plugin.debugBus case DEBUG_RISCV => {
assert(plugin.debugBus != null, "You need to enable CsrPluginConfig.withPrivilegedDebug")
debugRiscv <> plugin.debugBus
}
case _ => case _ =>
} }
} }