Hardware/VexRiscv
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3 commits

Author SHA1 Message Date
Dolu1990
0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990
594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990
8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00