Hardware/VexRiscv
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VexRiscv/src/test/scala/vexriscv
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Charles Papon 4f0a02594c Change LR/SC to reserve the whole memory 
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
2019-04-04 20:34:35 +02:00
..
experimental Fix mprv and add it into the softare model 2019-03-25 12:03:32 +01:00
DhrystoneBench.scala wip 2018-09-30 12:57:08 +02:00
MuraxSim.scala Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
TestIndividualFeatures.scala Change LR/SC to reserve the whole memory 2019-04-04 20:34:35 +02:00