xc7: add lite SATA example

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

xc7/litex_sata_demo/Makefile

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+current_dir := ${CURDIR}
+TOP := top
+SOURCES := ${current_dir}/litesata.v \
+           ${current_dir}/VexRiscv.v
+
+XDC := ${current_dir}/nexys_video.xdc
+
+include ${current_dir}/../../common/common.mk

xc7/litex_sata_demo/README.rst

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+LiteX SATA demo
+~~~~~~~~~~~~~~~
+
+This example design features a Litex SoC based around VexRiscv soft
+CPU. It also includes a DDR controller and a SATA core . To build the litex SATA example,
+run the following commands:
+
+To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run:
+
+
+.. code-block:: bash
+   :name: example-litex-sata-nexys-video-group
+
+   TARGET="nexys_video" make -C litex_sata_demo
+
+At completion, the bitstreams are located in the build directory:
+
+.. code-block:: bash
+
+   litex_sata_demo/build/<board>
+

xc7/litex_sata_demo/mem_2.init

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xc7/litex_sata_demo/nexys_video.xdc

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+################################################################################
+# IO constraints
+################################################################################
+# serial:0.tx
+set_property LOC AA19 [get_ports {serial_tx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}]
+
+# serial:0.rx
+set_property LOC V18 [get_ports {serial_rx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}]
+
+# cpu_reset:0
+set_property LOC G4 [get_ports {cpu_reset}]
+set_property IOSTANDARD LVCMOS15 [get_ports {cpu_reset}]
+
+# clk100:0
+set_property LOC R4 [get_ports {clk100}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk100}]
+
+# ddram:0.a
+set_property LOC M2 [get_ports {ddram_a[0]}]
+set_property SLEW FAST [get_ports {ddram_a[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
+
+# ddram:0.a
+set_property LOC M5 [get_ports {ddram_a[1]}]
+set_property SLEW FAST [get_ports {ddram_a[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
+
+# ddram:0.a
+set_property LOC M3 [get_ports {ddram_a[2]}]
+set_property SLEW FAST [get_ports {ddram_a[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
+
+# ddram:0.a
+set_property LOC M1 [get_ports {ddram_a[3]}]
+set_property SLEW FAST [get_ports {ddram_a[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
+
+# ddram:0.a
+set_property LOC L6 [get_ports {ddram_a[4]}]
+set_property SLEW FAST [get_ports {ddram_a[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
+
+# ddram:0.a
+set_property LOC P1 [get_ports {ddram_a[5]}]
+set_property SLEW FAST [get_ports {ddram_a[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
+
+# ddram:0.a
+set_property LOC N3 [get_ports {ddram_a[6]}]
+set_property SLEW FAST [get_ports {ddram_a[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
+
+# ddram:0.a
+set_property LOC N2 [get_ports {ddram_a[7]}]
+set_property SLEW FAST [get_ports {ddram_a[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
+
+# ddram:0.a
+set_property LOC M6 [get_ports {ddram_a[8]}]
+set_property SLEW FAST [get_ports {ddram_a[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
+
+# ddram:0.a
+set_property LOC R1 [get_ports {ddram_a[9]}]
+set_property SLEW FAST [get_ports {ddram_a[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
+
+# ddram:0.a
+set_property LOC L5 [get_ports {ddram_a[10]}]
+set_property SLEW FAST [get_ports {ddram_a[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
+
+# ddram:0.a
+set_property LOC N5 [get_ports {ddram_a[11]}]
+set_property SLEW FAST [get_ports {ddram_a[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
+
+# ddram:0.a
+set_property LOC N4 [get_ports {ddram_a[12]}]
+set_property SLEW FAST [get_ports {ddram_a[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
+
+# ddram:0.a
+set_property LOC P2 [get_ports {ddram_a[13]}]
+set_property SLEW FAST [get_ports {ddram_a[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
+
+# ddram:0.a
+set_property LOC P6 [get_ports {ddram_a[14]}]
+set_property SLEW FAST [get_ports {ddram_a[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
+
+# ddram:0.ba
+set_property LOC L3 [get_ports {ddram_ba[0]}]
+set_property SLEW FAST [get_ports {ddram_ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
+
+# ddram:0.ba
+set_property LOC K6 [get_ports {ddram_ba[1]}]
+set_property SLEW FAST [get_ports {ddram_ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
+
+# ddram:0.ba
+set_property LOC L4 [get_ports {ddram_ba[2]}]
+set_property SLEW FAST [get_ports {ddram_ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
+
+# ddram:0.ras_n
+set_property LOC J4 [get_ports {ddram_ras_n}]
+set_property SLEW FAST [get_ports {ddram_ras_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
+
+# ddram:0.cas_n
+set_property LOC K3 [get_ports {ddram_cas_n}]
+set_property SLEW FAST [get_ports {ddram_cas_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
+
+# ddram:0.we_n
+set_property LOC L1 [get_ports {ddram_we_n}]
+set_property SLEW FAST [get_ports {ddram_we_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
+
+# ddram:0.dm
+set_property LOC G3 [get_ports {ddram_dm[0]}]
+set_property SLEW FAST [get_ports {ddram_dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
+
+# ddram:0.dm
+set_property LOC F1 [get_ports {ddram_dm[1]}]
+set_property SLEW FAST [get_ports {ddram_dm[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
+
+# ddram:0.dq
+set_property LOC G2 [get_ports {ddram_dq[0]}]
+set_property SLEW FAST [get_ports {ddram_dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}]
+
+# ddram:0.dq
+set_property LOC H4 [get_ports {ddram_dq[1]}]
+set_property SLEW FAST [get_ports {ddram_dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}]
+
+# ddram:0.dq
+set_property LOC H5 [get_ports {ddram_dq[2]}]
+set_property SLEW FAST [get_ports {ddram_dq[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}]
+
+# ddram:0.dq
+set_property LOC J1 [get_ports {ddram_dq[3]}]
+set_property SLEW FAST [get_ports {ddram_dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}]
+
+# ddram:0.dq
+set_property LOC K1 [get_ports {ddram_dq[4]}]
+set_property SLEW FAST [get_ports {ddram_dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}]
+
+# ddram:0.dq
+set_property LOC H3 [get_ports {ddram_dq[5]}]
+set_property SLEW FAST [get_ports {ddram_dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}]
+
+# ddram:0.dq
+set_property LOC H2 [get_ports {ddram_dq[6]}]
+set_property SLEW FAST [get_ports {ddram_dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}]
+
+# ddram:0.dq
+set_property LOC J5 [get_ports {ddram_dq[7]}]
+set_property SLEW FAST [get_ports {ddram_dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}]
+
+# ddram:0.dq
+set_property LOC E3 [get_ports {ddram_dq[8]}]
+set_property SLEW FAST [get_ports {ddram_dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}]
+
+# ddram:0.dq
+set_property LOC B2 [get_ports {ddram_dq[9]}]
+set_property SLEW FAST [get_ports {ddram_dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}]
+
+# ddram:0.dq
+set_property LOC F3 [get_ports {ddram_dq[10]}]
+set_property SLEW FAST [get_ports {ddram_dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}]
+
+# ddram:0.dq
+set_property LOC D2 [get_ports {ddram_dq[11]}]
+set_property SLEW FAST [get_ports {ddram_dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}]
+
+# ddram:0.dq
+set_property LOC C2 [get_ports {ddram_dq[12]}]
+set_property SLEW FAST [get_ports {ddram_dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}]
+
+# ddram:0.dq
+set_property LOC A1 [get_ports {ddram_dq[13]}]
+set_property SLEW FAST [get_ports {ddram_dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}]
+
+# ddram:0.dq
+set_property LOC E2 [get_ports {ddram_dq[14]}]
+set_property SLEW FAST [get_ports {ddram_dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}]
+
+# ddram:0.dq
+set_property LOC B1 [get_ports {ddram_dq[15]}]
+set_property SLEW FAST [get_ports {ddram_dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}]
+
+# ddram:0.dqs_p
+set_property LOC K2 [get_ports {ddram_dqs_p[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
+
+# ddram:0.dqs_p
+set_property LOC E1 [get_ports {ddram_dqs_p[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
+
+# ddram:0.dqs_n
+set_property LOC J2 [get_ports {ddram_dqs_n[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
+
+# ddram:0.dqs_n
+set_property LOC D1 [get_ports {ddram_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
+
+# ddram:0.clk_p
+set_property LOC P5 [get_ports {ddram_clk_p}]
+set_property SLEW FAST [get_ports {ddram_clk_p}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
+
+# ddram:0.clk_n
+set_property LOC P4 [get_ports {ddram_clk_n}]
+set_property SLEW FAST [get_ports {ddram_clk_n}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
+
+# ddram:0.cke
+set_property LOC J6 [get_ports {ddram_cke}]
+set_property SLEW FAST [get_ports {ddram_cke}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
+
+# ddram:0.odt
+set_property LOC K4 [get_ports {ddram_odt}]
+set_property SLEW FAST [get_ports {ddram_odt}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
+
+# ddram:0.reset_n
+set_property LOC G1 [get_ports {ddram_reset_n}]
+set_property SLEW FAST [get_ports {ddram_reset_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}]
+
+# fmc2sata:0.clk_p
+set_property LOC F10 [get_ports {fmc2sata_clk_p}]
+
+# fmc2sata:0.clk_n
+set_property LOC E10 [get_ports {fmc2sata_clk_n}]
+
+# fmc2sata:0.tx_p
+set_property LOC D7 [get_ports {fmc2sata_tx_p}]
+
+# fmc2sata:0.tx_n
+set_property LOC C7 [get_ports {fmc2sata_tx_n}]
+
+# fmc2sata:0.rx_p
+set_property LOC D9 [get_ports {fmc2sata_rx_p}]
+
+# fmc2sata:0.rx_n
+set_property LOC C9 [get_ports {fmc2sata_rx_n}]
+
+# user_led:0
+set_property LOC T14 [get_ports {user_led0}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led0}]
+
+# user_led:1
+set_property LOC T15 [get_ports {user_led1}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led1}]
+
+# user_led:2
+set_property LOC T16 [get_ports {user_led2}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led2}]
+
+# user_led:3
+set_property LOC U16 [get_ports {user_led3}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led3}]
+
+# user_led:4
+set_property LOC V15 [get_ports {user_led4}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led4}]
+
+# user_led:5
+set_property LOC W16 [get_ports {user_led5}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led5}]
+
+# user_led:6
+set_property LOC W15 [get_ports {user_led6}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led6}]
+
+# user_led:7
+set_property LOC Y13 [get_ports {user_led7}]
+set_property IOSTANDARD LVCMOS25 [get_ports {user_led7}]
+
+# vadj:0
+set_property LOC AA13 [get_ports {vadj[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {vadj[0]}]
+
+# vadj:1
+set_property LOC AB17 [get_ports {vadj[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {vadj[1]}]
+
+################################################################################
+# Design constraints
+################################################################################
+
+set_property INTERNAL_VREF 0.750 [get_iobanks 35]
+
+################################################################################