Joshua Fife b8a300db26 Changed some formatting, made naming consistent, and clarified info on SystemVerilog ... Signed-off-by: Joshua Fife <jpfife17@gmail.com>		2021-06-30 09:21:21 -06:00
..
images	xc7: add picorv32 and vexriscv litex example	2021-06-18 09:31:25 +02:00
master_makefile	Added instructions for Makefile	2021-06-08 17:59:33 -06:00
templates	docs: Initial Sphinx setup	2020-12-11 10:34:04 +01:00
.gitattributes	docs: Initial Sphinx setup	2020-12-11 10:34:04 +01:00
.gitignore	docs: Initial Sphinx setup	2020-12-11 10:34:04 +01:00
Makefile	Add license headers to docs and CI scripts	2020-12-14 14:45:55 +01:00
building-examples.rst	Fixed merge conflict	2021-06-26 18:43:21 -06:00
collect_readmes.py	formatted files	2021-05-13 12:07:40 -06:00
conf.py	changes after initial review	2021-05-13 12:07:04 -06:00
customizing-makefiles.rst	Changed some formatting, made naming consistent, and clarified info on SystemVerilog	2021-06-30 09:21:21 -06:00
getting-symbiflow.rst	xc7: update packages	2021-03-26 14:52:22 +01:00
index.rst	Changed some formatting, made naming consistent, and clarified info on SystemVerilog	2021-06-30 09:21:21 -06:00
personal-designs.rst	Changed some formatting, made naming consistent, and clarified info on SystemVerilog	2021-06-30 09:21:21 -06:00
requirements.txt	docs: Initial Sphinx setup	2020-12-11 10:34:04 +01:00
running-examples.rst	fix typos	2021-01-09 20:09:46 +00:00