2018-08-31 17:20:47 -04:00
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from litedram.modules import MT41K128M16
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from litedram.phy import A7DDRPHY
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core_config = {
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# cpu
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"cpu": "picorv32",
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# modules / phy
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"sdram_module": MT41K128M16,
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"sdram_module_nb": 1,
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2018-10-01 05:48:15 -04:00
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"sdram_module_speedgrade": "1066",
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2018-09-07 11:55:46 -04:00
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"sdram_rank_nb": 1,
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2018-08-31 17:20:47 -04:00
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"sdram_phy": A7DDRPHY,
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# electrical
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"rtt_nom": "60ohm",
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"rtt_wr": "60ohm",
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"ron": "34ohm",
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# freqs
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"input_clk_freq": 100e6,
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"sys_clk_freq": 100e6,
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"iodelay_clk_freq": 200e6,
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# controller
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"cmd_buffer_depth": 16,
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"write_time": 16,
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"read_time": 32,
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# user_ports
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"user_ports_nb": 1,
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2018-09-07 11:55:46 -04:00
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"user_ports_type": "axi",
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"user_ports_id_width": 8
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2018-08-31 17:20:47 -04:00
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}
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