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gen: Rename standalone core wishbone 

Name it wb_ctrl rather than just wb, which makes the resulting
core signal names a bit more descriptive. IE. The DRAM control
bus (by opposition to the use/data buss(es).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-05-12 21:59:01 +10:00
parent b0838f70e3
commit 04717b478b
1 changed files with 3 additions and 3 deletions
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6
litedram/gen.py
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@ -381,10 +381,10 @@ class LiteDRAMCore(SoCCore):
] ]
if cpu_type is None: if cpu_type is None:
# Expose bus interface to user. # Expose bus interface to user.
wb_bus = wishbone.Interface() wb_bus = wishbone.Interface(adr_width = self.csr.address_width)
self.bus.add_master(master=wb_bus) self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb")) platform.add_extension(wb_bus.get_ios("wb_ctrl"))
wb_pads = platform.request("wb") wb_pads = platform.request("wb_ctrl")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# User ports ------------------------------------------------------------------------------- # User ports -------------------------------------------------------------------------------