Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

init: Enable DQ-DQS training on 7-Series (except Artix7) and Ultrascale.

This commit is contained in:
Florent Kermarrec 2021-04-22 18:34:18 +02:00
parent 3f4b6f661c
commit 103534d0e8
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litedram/init.py
View File

@ -689,13 +689,12 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
"K7DDRPHY", "V7DDRPHY", "K7DDRPHY", "V7DDRPHY",
"K7LPDDR4PHY", "V7LPDDR4PHY"]: "K7LPDDR4PHY", "V7LPDDR4PHY"]:
r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n" r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
if phytype in ["USDDRPHY", "USPDDRPHY", if phytype in ["USDDRPHY", "USPDDRPHY",
"A7DDRPHY", "K7DDRPHY", "V7DDRPHY", "A7DDRPHY", "K7DDRPHY", "V7DDRPHY",
"A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]: "A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n" r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
if phytype in ["K7LPDDR4PHY", "V7LPDDR4PHY"]:
r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
if phytype in ["ECP5DDRPHY"]: if phytype in ["ECP5DDRPHY"]:
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
if phytype in ["LPDDR4SIMPHY"]: if phytype in ["LPDDR4SIMPHY"]: