frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI

2018-11-26 10:37:28 +01:00 · 2018-11-26 10:37:28 +01:00 · 170b3dc67d
parent 9a255062e0
commit 170b3dc67d
1 changed files with 2 additions and 0 deletions
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@ -66,6 +66,7 @@ class LiteDRAMWishbone2AXI(Module):
            )
        )
        fsm.act("WRITE",
+            port.aw.size.eq(ashift),
            port.aw.addr[ashift:].eq(wishbone.adr),
            port.w.last.eq(1),
            port.w.data.eq(wishbone.dat_w),
@ -84,6 +85,7 @@ class LiteDRAMWishbone2AXI(Module):
            )
        )
        fsm.act("READ",
+            port.ar.size.eq(ashift),
            port.ar.addr[ashift:].eq(wishbone.adr),
            If(port.ar.ready,
                NextValue(port.ar.valid, 0)