frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI

2018-11-26 08:56:00 +01:00 · 2018-11-26 08:56:00 +01:00 · 9a255062e0
parent bc6a3f220a
commit 9a255062e0
1 changed files with 1 additions and 1 deletions
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@ -92,7 +92,7 @@ class LiteDRAMWishbone2AXI(Module):
                port.r.ready.eq(1),
                wishbone.dat_r.eq(port.r.data),
                wishbone.ack.eq(1),
-                wishbone.err.eq(port.r.resp != 0b10),
+                wishbone.err.eq(port.r.resp != 0b00),
                NextState("IDLE")
            )
        )