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phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits

This commit is contained in:
Florent Kermarrec 2019-06-22 10:46:02 +02:00
parent 690e4f848f
commit 18dda2db54
1 changed files with 1 additions and 1 deletions
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2
litedram/phy/s7ddrphy.py
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@ -62,7 +62,7 @@ class S7DDRPHY(Module, AutoCSR):
}
half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
self._half_sys8x_taps = CSRStorage(4, reset=half_sys8x_taps)
self._half_sys8x_taps = CSRStorage(5, reset=half_sys8x_taps)
if with_odelay:
self._wlevel_en = CSRStorage()