Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litedram_gen: pass FPGA speedgrade to iodelay_pll.

This commit is contained in:
Florent Kermarrec 2020-05-14 11:44:32 +02:00
parent f4871b9f13
commit 1f7d9eb0b9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litedram/gen.py
View File

@ -280,7 +280,7 @@ class LiteDRAMS7DDRPHYCRG(Module):
sys_pll.create_clkout(self.cd_sys2x_dqs, 2*core_config["sys_clk_freq"], phase=90) sys_pll.create_clkout(self.cd_sys2x_dqs, 2*core_config["sys_clk_freq"], phase=90)
self.comb += platform.request("pll_locked").eq(sys_pll.locked) self.comb += platform.request("pll_locked").eq(sys_pll.locked)
self.submodules.iodelay_pll = iodelay_pll = S7PLL() self.submodules.iodelay_pll = iodelay_pll = S7PLL(speedgrade=core_config["speedgrade"])
self.comb += iodelay_pll.reset.eq(rst) self.comb += iodelay_pll.reset.eq(rst)
iodelay_pll.register_clkin(clk, core_config["input_clk_freq"]) iodelay_pll.register_clkin(clk, core_config["input_clk_freq"])
iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"]) iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])