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litedram_gen: avoid second S7PLL for iodelay clk, generate it from main S7PLL on CLKOUT0 (with fractional divide).

This commit is contained in:
Florent Kermarrec 2020-06-03 09:04:00 +02:00
parent 1b56dcf364
commit 361d250677
1 changed files with 1 additions and 4 deletions
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5
litedram/gen.py
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@ -277,6 +277,7 @@ class LiteDRAMS7DDRPHYCRG(Module):
self.submodules.sys_pll = sys_pll = S7PLL(speedgrade=core_config["speedgrade"])
self.comb += sys_pll.reset.eq(rst)
sys_pll.register_clkin(clk, core_config["input_clk_freq"])
sys_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
sys_pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"])
if core_config["memtype"] == "DDR2":
sys_pll.create_clkout(self.cd_sys2x, 2*core_config["sys_clk_freq"])
@ -289,10 +290,6 @@ class LiteDRAMS7DDRPHYCRG(Module):
self.comb += platform.request("pll_locked").eq(sys_pll.locked)
self.submodules.iodelay_pll = iodelay_pll = S7PLL(speedgrade=core_config["speedgrade"])
self.comb += iodelay_pll.reset.eq(rst)
iodelay_pll.register_clkin(clk, core_config["input_clk_freq"])
iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay)
# LiteDRAMCoreControl ------------------------------------------------------------------------------