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test: correct DMAReaderDriver/DMAWriterDriver logic

This commit is contained in:
Jędrzej Boczar 2020-03-17 15:37:50 +01:00
parent 6ef623efae
commit 36d5b42aa0
1 changed files with 4 additions and 8 deletions
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12
test/test_bist.py
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@ -95,8 +95,7 @@ class DMAWriterDriver:
yield self.dma.sink.data.eq(data) yield self.dma.sink.data.eq(data)
while not (yield self.dma.sink.ready): while not (yield self.dma.sink.ready):
yield yield
while (yield self.dma.sink.ready): yield
yield
yield self.dma.sink.valid.eq(0) yield self.dma.sink.valid.eq(0)
@staticmethod @staticmethod
@ -104,8 +103,7 @@ class DMAWriterDriver:
for _ in range(n): for _ in range(n):
while not (yield port.wdata.ready): while not (yield port.wdata.ready):
yield yield
while (yield port.wdata.ready): yield
yield
class DMAReaderDriver: class DMAReaderDriver:
@ -130,10 +128,8 @@ class DMAReaderDriver:
def read_handler(self): def read_handler(self):
yield self.dma.source.ready.eq(1) yield self.dma.source.ready.eq(1)
while True: while True:
while not (yield self.dma.source.valid): if (yield self.dma.source.valid):
yield self.data.append((yield self.dma.source.data))
data = (yield self.dma.source.data)
self.data.append(data)
yield yield