phy/s7ddrphy: fix dqs_sys_latency for DDR2

2018-09-03 12:21:04 +02:00 · 2018-09-03 12:21:04 +02:00 · 6017e7a763
parent 7b427391bd
commit 6017e7a763
1 changed files with 4 additions and 1 deletions
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@ -406,7 +406,10 @@ class S7DDRPHY(Module, AutoCSR):
            ]

        # dqs preamble/postamble
-        dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
+        if memtype == "DDR2":
+            dqs_sys_latency = cwl_sys_latency-1
+        elif memtype == "DDR3":
+            dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
        self.comb += [
            dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
                            ~last_wrdata_en[dqs_sys_latency]),