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frontend/bist: use new reset_less attribute where possible

This commit is contained in:
Florent Kermarrec 2017-06-29 11:20:08 +02:00
parent c8713bfb48
commit 67df00bcac
1 changed files with 3 additions and 3 deletions
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6
litedram/frontend/bist.py
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@ -86,7 +86,7 @@ class _LiteDRAMBISTGenerator(Module):
dma = LiteDRAMDMAWriter(dram_port) dma = LiteDRAMDMAWriter(dram_port)
self.submodules += dma, gen self.submodules += dma, gen
cmd_counter = Signal(dram_port.aw) cmd_counter = Signal(dram_port.aw, reset_less=True)
fsm = FSM(reset_state="IDLE") fsm = FSM(reset_state="IDLE")
self.submodules += fsm self.submodules += fsm
@ -209,7 +209,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.submodules += dma, gen self.submodules += dma, gen
# address # address
cmd_counter = Signal(dram_port.aw) cmd_counter = Signal(dram_port.aw, reset_less=True)
cmd_fsm = FSM(reset_state="IDLE") cmd_fsm = FSM(reset_state="IDLE")
self.submodules += cmd_fsm self.submodules += cmd_fsm
@ -232,7 +232,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.comb += dma.sink.address.eq(self.base + cmd_counter) self.comb += dma.sink.address.eq(self.base + cmd_counter)
# data # data
data_counter = Signal(dram_port.aw) data_counter = Signal(dram_port.aw, reset_less=True)
data_fsm = FSM(reset_state="IDLE") data_fsm = FSM(reset_state="IDLE")
self.submodules += data_fsm self.submodules += data_fsm