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Merge pull request #226 from mdpye/MT48LC32M8 

modules: add MT48LC32M8 SDR module
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enjoy-digital 2021-01-03 22:13:19 +01:00 committed by GitHub
parent 103072c68a ec37a6353b
commit 87f95f8442
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litedram/modules.py
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@ -461,6 +461,15 @@ class MT48LC16M16(SDRModule):
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15)) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
class MT48LC32M8(SDRModule):
# geometry
nbanks = 4
nrows = 8192
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
class AS4C16M16(SDRModule): class AS4C16M16(SDRModule):
# geometry # geometry
nbanks = 4 nbanks = 4