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phy/ecp5ddrphy: fix dqs preamble/postamble control. (make it similar to 7-series/Ultrascale).

This commit is contained in:
Florent Kermarrec 2020-04-16 15:29:02 +02:00
parent 5d29686b1a
commit 91a9a2aeb1
1 changed files with 2 additions and 2 deletions
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4
litedram/phy/ecp5ddrphy.py
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@ -479,5 +479,5 @@ class ECP5DDRPHY(Module, AutoCSR):
# Write DQS Postamble/Preamble Control Path ------------------------------------------------
# Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
# write.
self.sync += dqs_preamble.eq(wrdata_en[cwl_sys_latency - 1])
self.sync += dqs_postamble.eq(oe_dqs)
self.sync += dqs_preamble.eq( wrdata_en[cwl_sys_latency:-1] == 0b10)
self.sync += dqs_postamble.eq(wrdata_en[cwl_sys_latency+1:] == 0b01)