Merge pull request #142 from antmicro/updated-trefi-verifier
Update tREFI verifier
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commit
95b827d435
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@ -223,6 +223,7 @@ class DFITimingsChecker(Module):
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self.timings = new_timings
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def __init__(self, dfi, nbanks, nphases, timings, refresh_mode, memtype, verbose=False):
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ref_limit = {"1x": 9, "2x": 17, "4x": 36}
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self.prepare_timings(timings, refresh_mode, memtype)
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self.add_cmds()
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self.add_rules()
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@ -297,13 +298,39 @@ class DFITimingsChecker(Module):
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# tREFI
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ref_ps = Signal().like(cnt)
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ref_ps_mod = Signal().like(cnt)
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ref_ps_diff = Signal(min=-2**63, max=2**63)
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curr_diff = Signal().like(ref_ps_diff)
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self.comb += curr_diff.eq(ps - (ref_ps + self.timings["tREFI"]))
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# Work in 64ms periods
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self.sync += If(ref_ps_mod < int(64e9),
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ref_ps_mod.eq(ref_ps_mod + nphases * self.timings["tCK"])).Else(ref_ps_mod.eq(0))
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# Update timestamp and difference
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self.sync += If(ref_issued != 0, ref_ps.eq(ps), ref_ps_diff.eq(ref_ps_diff - curr_diff))
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self.sync += If((ref_ps_mod == 0) & (ref_ps_diff > 0),
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Display("[%016dps] tREFI violation (64ms period): %0d", ps, ref_ps_diff))
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# Report any refresh periods longer than tREFI
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if verbose:
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ref_done = Signal()
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self.sync += If(ref_issued != 0, ref_ps.eq(ps), ref_done.eq(1),
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self.sync += If(ref_issued != 0, ref_done.eq(1),
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If(~ref_done, Display("[%016dps] Late refresh", ps)))
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self.sync += If((ps > (ref_ps + self.timings["tREFI"])) & ref_done & (ref_issued == 0),
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self.sync += If((curr_diff > 0) & ref_done & (ref_issued == 0),
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Display("[%016dps] tREFI violation", ps), ref_done.eq(0))
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# There is a maximum delay between refreshes on >=DDR
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if memtype != "SDR":
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refresh_mode = "1x" if refresh_mode is None else refresh_mode
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ref_done = Signal()
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self.sync += If(ref_issued != 0, ref_done.eq(1))
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self.sync += If((ref_issued == 0) & ref_done & (ref_ps > (ps + ref_limit[refresh_mode] * self.timings['tREFI'])),
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Display("[%016dps] tREFI violation (too many postponed refreshes)", ps), ref_done.eq(0))
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# SDRAM PHY Model ----------------------------------------------------------------------------------
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class SDRAMPHYModel(Module):
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