frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI
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@ -92,7 +92,7 @@ class LiteDRAMWishbone2AXI(Module):
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port.r.ready.eq(1),
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port.r.ready.eq(1),
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wishbone.dat_r.eq(port.r.data),
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wishbone.dat_r.eq(port.r.data),
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wishbone.ack.eq(1),
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wishbone.ack.eq(1),
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wishbone.err.eq(port.r.resp != 0b10),
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wishbone.err.eq(port.r.resp != 0b00),
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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)
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)
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