Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation

This commit is contained in:
Florent Kermarrec 2018-09-15 01:50:53 +02:00
parent 5719d71ace
commit a8d26724dd
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litedram/phy/s7ddrphy_halfrate_bl8.py
View File

@ -444,10 +444,10 @@ class S7DDRPHY(Module, AutoCSR):
elif memtype == "DDR3":
dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
self.comb += [
dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
~last_wrdata_en[dqs_sys_latency]),
dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+2] &
~last_wrdata_en[dqs_sys_latency+1]),
#dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
# ~last_wrdata_en[dqs_sys_latency]),
#dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+2] &
# ~last_wrdata_en[dqs_sys_latency+1]),
]