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We had the address and data bus sizes mixed up 

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2019-09-23 08:50:25 +02:00 committed by Florent Kermarrec
parent d93dded624
commit afbf709767
1 changed files with 3 additions and 1 deletions
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litedram/gen.py
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@ -290,7 +290,9 @@ class LiteDRAMCore(SoCSDRAM):
# CSR port # CSR port
if core_config.get("expose_csr_port", "no") == "yes": if core_config.get("expose_csr_port", "no") == "yes":
csr_port = csr_bus.Interface(self.csr_address_width, self.csr_data_width) csr_port = csr_bus.Interface(
address_width=self.csr_address_width,
data_width=self.csr_data_width)
self.add_csr_master(csr_port) self.add_csr_master(csr_port)
platform.add_extension(get_csr_ios(self.csr_address_width, platform.add_extension(get_csr_ios(self.csr_address_width,
self.csr_data_width)) self.csr_data_width))