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modules/H5TC4G63CFR: cleanup

This commit is contained in:
Florent Kermarrec 2020-01-13 17:05:46 +01:00
parent 7d8287b57a
commit b77af48d50
1 changed files with 2 additions and 1 deletions
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3
litedram/modules.py
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@ -375,6 +375,7 @@ class K4B2G1646F(SDRAMModule):
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
class H5TC4G63CFR(SDRAMModule):
memtype = "DDR3"
# geometry
@ -384,7 +385,7 @@ class H5TC4G63CFR(SDRAMModule):
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 7.5), tZQCS=(64, 80))
speedgrade_timings = {
"800": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5),
"800": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5),
}
speedgrade_timings["default"] = speedgrade_timings["800"]