modules/H5TC4G63CFR: cleanup

2020-01-13 17:05:46 +01:00 · 2020-01-13 17:05:46 +01:00 · b77af48d50
parent 7d8287b57a
commit b77af48d50
1 changed files with 2 additions and 1 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -375,6 +375,7 @@ class K4B2G1646F(SDRAMModule):
    }
    speedgrade_timings["default"] = speedgrade_timings["1600"]

+
 class H5TC4G63CFR(SDRAMModule):
    memtype = "DDR3"
    # geometry