lpddr5: wck sync at every transaction
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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@ -704,7 +704,7 @@ def get_lpddr5_phy_init_sequence(phy_settings, timing_settings):
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mr[18] = reg([
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(0, 3, rzq_map[wck_odt]),
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(3, 1, 0), # WCK low frequency mode
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(4, 1, 1), # WCK always on mode enabled
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(4, 1, 0), # WCK always on mode enabled
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(6, 1, 0), # WCK2CK leveling diabled
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(7, 1, {2: 1, 4: 0}[wck_ck_ratio]),
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])
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@ -121,7 +121,6 @@ def get_frange(twck, wck_ck_ratio):
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return frange
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raise ValueError
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class LPDDR5PHY(Module, AutoCSR):
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"""Core logic of LPDDR5 PHY
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@ -295,9 +294,6 @@ class LPDDR5PHY(Module, AutoCSR):
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# WL = tWCKENL_WR - 1 + tWCKPRE_Static + tWCKPRE_Toggle_WR
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# RL = tWCKENL_RD - 1 + tWCKPRE_Static + tWCKPRE_Toggle_RD (without Byte Mode, nor Read DBI/Read Data Copy)
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wck_sync_done = Signal()
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self.sync += If(self.adapter.wck_sync != 0, wck_sync_done.eq(1))
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self.comb += self.adapter.wck_sync_done.eq(wck_sync_done)
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wck_sync = TappedDelayLine(
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signal = self.adapter.wck_sync,
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ntaps = max(1, max(frange.t_wckenl_wr, frange.t_wckenl_rd) + frange.t_wckpre_static),
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@ -428,6 +424,24 @@ class LPDDR5PHY(Module, AutoCSR):
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self.dfi.p0.rddata_valid.eq(rddata_converter.source.valid),
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]
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self.wck_sync_state = Signal(2)
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self.sync += If(self.adapter.wck_sync != 0,
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wck_sync_done.eq(1),
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self.wck_sync_state.eq(self.adapter.wck_sync)
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).Elif(self.wck_sync_state == WCKSyncType.RD,
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If(reduce(or_, rddata_en.taps[0:rddata_start+burst_ck_cycles]) == 0,
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wck_sync_done.eq(0),
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self.wck_sync_state.eq(0b00),
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)
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).Elif(self.wck_sync_state == WCKSyncType.WR,
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If(reduce(or_, wrdata_en.taps[0:wrtap+burst_ck_cycles]) == 0,
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wck_sync_done.eq(0),
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self.wck_sync_state.eq(0b00),
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)
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)
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self.comb += self.adapter.wck_sync_done.eq(wck_sync_done)
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for bit in range(self.databits):
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# output
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wrdata = [wrdata_ck[i * self.databits + bit] for i in range(2*wck_ck_ratio)]
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