Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS.

This commit is contained in:
Florent Kermarrec 2022-09-08 16:03:39 +02:00
parent 5b72d1a34a
commit cff8500f52
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litedram/phy/gw2ddrphy.py
View File

@ -195,6 +195,7 @@ class GW2DDRPHY(Module, AutoCSR):
pad_oddrx2f = Signal() pad_oddrx2f = Signal()
pad_clk = Signal() pad_clk = Signal()
self.specials += Instance("OSER4", self.specials += Instance("OSER4",
p_TXCLK_POL = 0b0,
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
i_PCLK = ClockSignal("sys"), i_PCLK = ClockSignal("sys"),
i_FCLK = ClockSignal("sys2x"), i_FCLK = ClockSignal("sys2x"),
@ -238,6 +239,7 @@ class GW2DDRPHY(Module, AutoCSR):
for i in range(len(pad)): for i in range(len(pad)):
pad_oddrx2f = Signal() pad_oddrx2f = Signal()
self.specials += Instance("OSER4", self.specials += Instance("OSER4",
p_TXCLK_POL = 0b0,
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
i_PCLK = ClockSignal("sys"), i_PCLK = ClockSignal("sys"),
i_FCLK = ClockSignal("sys2x"), i_FCLK = ClockSignal("sys2x"),
@ -320,6 +322,7 @@ class GW2DDRPHY(Module, AutoCSR):
self.specials += [ self.specials += [
Instance("OSER4_MEM", Instance("OSER4_MEM",
p_TCLK_SOURCE = "DQSW", p_TCLK_SOURCE = "DQSW",
p_TXCLK_POL = 0b1,
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
i_PCLK = ClockSignal("sys"), i_PCLK = ClockSignal("sys"),
i_FCLK = ClockSignal("sys2x"), i_FCLK = ClockSignal("sys2x"),
@ -352,6 +355,7 @@ class GW2DDRPHY(Module, AutoCSR):
self.sync += Case(bl8_chunk, dm_bl8_cases) self.sync += Case(bl8_chunk, dm_bl8_cases)
self.specials += Instance("OSER4_MEM", self.specials += Instance("OSER4_MEM",
p_TCLK_SOURCE = "DQSW270", p_TCLK_SOURCE = "DQSW270",
p_TXCLK_POL = 0b0,
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
i_PCLK = ClockSignal("sys"), i_PCLK = ClockSignal("sys"),
i_FCLK = ClockSignal("sys2x"), i_FCLK = ClockSignal("sys2x"),
@ -380,6 +384,7 @@ class GW2DDRPHY(Module, AutoCSR):
self.specials += [ self.specials += [
Instance("OSER4_MEM", Instance("OSER4_MEM",
p_TCLK_SOURCE = "DQSW270", p_TCLK_SOURCE = "DQSW270",
p_TXCLK_POL = 0b0,
i_RESET = ResetSignal("sys"), i_RESET = ResetSignal("sys"),
i_PCLK = ClockSignal("sys"), i_PCLK = ClockSignal("sys"),
i_FCLK = ClockSignal("sys2x"), i_FCLK = ClockSignal("sys2x"),