phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS.
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parent
5b72d1a34a
commit
cff8500f52
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@ -195,6 +195,7 @@ class GW2DDRPHY(Module, AutoCSR):
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pad_oddrx2f = Signal()
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pad_clk = Signal()
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self.specials += Instance("OSER4",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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@ -238,6 +239,7 @@ class GW2DDRPHY(Module, AutoCSR):
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for i in range(len(pad)):
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pad_oddrx2f = Signal()
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self.specials += Instance("OSER4",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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@ -320,6 +322,7 @@ class GW2DDRPHY(Module, AutoCSR):
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self.specials += [
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Instance("OSER4_MEM",
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p_TCLK_SOURCE = "DQSW",
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p_TXCLK_POL = 0b1,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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@ -352,6 +355,7 @@ class GW2DDRPHY(Module, AutoCSR):
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self.sync += Case(bl8_chunk, dm_bl8_cases)
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self.specials += Instance("OSER4_MEM",
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p_TCLK_SOURCE = "DQSW270",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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@ -380,6 +384,7 @@ class GW2DDRPHY(Module, AutoCSR):
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self.specials += [
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Instance("OSER4_MEM",
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p_TCLK_SOURCE = "DQSW270",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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