gen: fix with_wishbone

2019-09-23 15:54:53 +02:00 · 2019-09-23 15:54:53 +02:00 · d647abd026
parent db97203877
commit d647abd026
1 changed files with 1 additions and 1 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -258,7 +258,7 @@ class LiteDRAMCore(SoCSDRAM):
            kwargs["with_uart"]            = False
            kwargs["with_timer"]           = False
            kwargs["with_ctrl"]            = False
-            kwargs["with_wishbone"]        = (cpu_type is None)
+            kwargs["with_wishbone"]        = (cpu_type != None)
        else:
           kwargs["l2_size"] = 0
        SoCSDRAM.__init__(self, platform, sys_clk_freq,