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phy/usddrphy: reduce BitSlip cycles to 1 sys_clk. 

Increasing it to 2 hasn't been useful.
This commit is contained in:
Florent Kermarrec 2020-09-24 13:36:02 +02:00
parent 06544c6547
commit db54e325c8
2 changed files with 2 additions and 2 deletions
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2
litedram/init.py
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@ -502,7 +502,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
if phytype in ["USDDRPHY", "USPDDRPHY"]:
r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
r += "#define SDRAM_PHY_DELAYS 512\n"
r += "#define SDRAM_PHY_BITSLIPS 16\n"
r += "#define SDRAM_PHY_BITSLIPS 8\n"
elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
r += "#define SDRAM_PHY_DELAYS 32\n"

2
litedram/phy/usddrphy.py
View File

@ -425,7 +425,7 @@ class USDDRPHY(Module, AutoCSR):
dq_bitslip = BitSlip(8,
rst = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip_rst.re,
slp = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip.re,
cycles = 2)
cycles = 1)
self.submodules += dq_bitslip
self.specials += [
Instance("OSERDESE3",