frontend/axi: move AXIBurst2Beat to LiteX
Will be useful for others purposes.
This commit is contained in:
Florent Kermarrec
parent
be269da3fe
commit
e824288924
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@ -26,69 +26,6 @@ class LiteDRAMAXIPort(AXIInterface):
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pass
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class LiteDRAMAXIBurst2Beat(Module):
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def __init__(self, ax_burst, ax_beat):
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# # #
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self.count = count = Signal(8)
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size = Signal(8 + 4)
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offset = Signal(8 + 4)
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# convert burst size to bytes
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cases = {}
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cases["default"] = size.eq(1024)
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for i in range(10):
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cases[i] = size.eq(2**i)
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self.comb += Case(ax_burst.size, cases)
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# fsm
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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ax_beat.valid.eq(ax_burst.valid),
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ax_beat.first.eq(1),
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ax_beat.last.eq(ax_burst.len == 0),
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ax_beat.addr.eq(ax_burst.addr),
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ax_beat.id.eq(ax_burst.id),
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If(ax_beat.valid & ax_beat.ready,
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If(ax_burst.len != 0,
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NextState("BURST2BEAT")
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).Else(
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ax_burst.ready.eq(1)
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)
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),
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NextValue(count, 1),
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NextValue(offset, size),
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)
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wrap_offset = Signal(8 + 4)
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self.sync += wrap_offset.eq((ax_burst.len - 1)*size)
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fsm.act("BURST2BEAT",
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ax_beat.valid.eq(1),
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ax_beat.first.eq(0),
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ax_beat.last.eq(count == ax_burst.len),
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If((ax_burst.burst == BURST_INCR) |
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(ax_burst.burst == BURST_WRAP),
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ax_beat.addr.eq(ax_burst.addr + offset)
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).Else(
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ax_beat.addr.eq(ax_burst.addr)
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),
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ax_beat.id.eq(ax_burst.id),
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If(ax_beat.valid & ax_beat.ready,
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If(ax_beat.last,
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ax_burst.ready.eq(1),
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NextState("IDLE")
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),
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NextValue(count, count + 1),
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NextValue(offset, offset + size),
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If(ax_burst.burst == BURST_WRAP,
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If(offset == wrap_offset,
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NextValue(offset, 0)
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)
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)
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)
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)
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class LiteDRAMAXI2NativeW(Module):
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def __init__(self, axi, port, buffer_depth):
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self.cmd_request = Signal()
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@ -103,7 +40,7 @@ class LiteDRAMAXI2NativeW(Module):
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self.submodules += aw_buffer
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self.comb += axi.aw.connect(aw_buffer.sink)
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aw = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
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aw_burst2beat = LiteDRAMAXIBurst2Beat(aw_buffer.source, aw)
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aw_burst2beat = AXIBurst2Beat(aw_buffer.source, aw)
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self.submodules.aw_burst2beat = aw_burst2beat
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# Write Buffer
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@ -171,7 +108,7 @@ class LiteDRAMAXI2NativeR(Module):
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self.submodules += ar_buffer
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self.comb += axi.ar.connect(ar_buffer.sink)
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ar = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
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ar_burst2beat = LiteDRAMAXIBurst2Beat(ar_buffer.source, ar)
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ar_burst2beat = AXIBurst2Beat(ar_buffer.source, ar)
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self.submodules.ar_burst2beat = ar_burst2beat
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# Read buffer
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@ -53,65 +53,6 @@ class Read(Access):
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class TestAXI(unittest.TestCase):
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def test_burst2beat(self):
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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yield ax.valid.eq(1)
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yield ax.addr.eq(burst.addr)
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yield ax.burst.eq(burst.type)
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yield ax.len.eq(burst.len)
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yield ax.size.eq(burst.size)
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while (yield ax.ready) == 0:
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yield
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yield ax.valid.eq(0)
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while prng.randrange(100) < valid_rand:
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yield
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yield
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@passive
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def beats_checker(ax, beats, ready_rand=50):
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self.errors = 0
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yield ax.ready.eq(0)
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prng = random.Random(42)
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for beat in beats:
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while ((yield ax.valid) and (yield ax.ready)) == 0:
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if prng.randrange(100) > ready_rand:
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yield ax.ready.eq(1)
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else:
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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# dut
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ax_burst = stream.Endpoint(ax_description(32, 32))
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ax_beat = stream.Endpoint(ax_description(32, 32))
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dut = LiteDRAMAXIBurst2Beat(ax_burst, ax_beat)
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# generate dut input (bursts)
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
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# generate expexted dut output (beats for reference)
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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]
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run_simulation(dut, generators)
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self.assertEqual(self.errors, 0)
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def _test_axi2native(self,
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naccesses=16, simultaneous_writes_reads=False,
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# rand_level: 0: min (no random), 100: max.
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