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Merge pull request #195 from enjoy-digital/bios-libs 

Init: Generate DFII defines in sdram_phy.h
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enjoy-digital 2020-05-19 08:18:38 +02:00 committed by GitHub
parent 5078b19bff fe48a9290c
commit e95af3f15b
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 53 additions and 4 deletions
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18
litedram/init.py
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@ -448,7 +448,23 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
def get_sdram_phy_c_header(phy_settings, timing_settings): def get_sdram_phy_c_header(phy_settings, timing_settings):
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n" r += "#include <hw/common.h>\n"
r += "#include <generated/csr.h>\n"
r += "\n"
r += "#define DFII_CONTROL_SEL 0x01\n"
r += "#define DFII_CONTROL_CKE 0x02\n"
r += "#define DFII_CONTROL_ODT 0x04\n"
r += "#define DFII_CONTROL_RESET_N 0x08\n"
r += "\n"
r += "#define DFII_COMMAND_CS 0x01\n"
r += "#define DFII_COMMAND_WE 0x02\n"
r += "#define DFII_COMMAND_CAS 0x04\n"
r += "#define DFII_COMMAND_RAS 0x08\n"
r += "#define DFII_COMMAND_WRDATA 0x10\n"
r += "#define DFII_COMMAND_RDDATA 0x20\n"
r += "\n"
phytype = phy_settings.phytype.upper() phytype = phy_settings.phytype.upper()
nphases = phy_settings.nphases nphases = phy_settings.nphases

13
test/reference/ddr3_init.h
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@ -2,7 +2,18 @@
#define __GENERATED_SDRAM_PHY_H #define __GENERATED_SDRAM_PHY_H
#include <hw/common.h> #include <hw/common.h>
#include <generated/csr.h> #include <generated/csr.h>
#include <hw/flags.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_K7DDRPHY #define SDRAM_PHY_K7DDRPHY
#define SDRAM_PHY_PHASES 4 #define SDRAM_PHY_PHASES 4

13
test/reference/ddr4_init.h
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@ -2,7 +2,18 @@
#define __GENERATED_SDRAM_PHY_H #define __GENERATED_SDRAM_PHY_H
#include <hw/common.h> #include <hw/common.h>
#include <generated/csr.h> #include <generated/csr.h>
#include <hw/flags.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_USDDRPHY #define SDRAM_PHY_USDDRPHY
#define SDRAM_PHY_PHASES 4 #define SDRAM_PHY_PHASES 4

13
test/reference/sdr_init.h
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@ -2,7 +2,18 @@
#define __GENERATED_SDRAM_PHY_H #define __GENERATED_SDRAM_PHY_H
#include <hw/common.h> #include <hw/common.h>
#include <generated/csr.h> #include <generated/csr.h>
#include <hw/flags.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_GENSDRPHY #define SDRAM_PHY_GENSDRPHY
#define SDRAM_PHY_PHASES 1 #define SDRAM_PHY_PHASES 1