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test: move DRAMMemory model to common

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This commit is contained in:
Florent Kermarrec 2016-05-23 13:30:38 +02:00
parent 94d526a78c
commit f36c65b66f
2 changed files with 55 additions and 54 deletions
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56
test/bist_tb.py
View file

@ -6,6 +6,8 @@ from litedram.common import LiteDRAMPort
from litedram.frontend.bist import LiteDRAMBISTGenerator from litedram.frontend.bist import LiteDRAMBISTGenerator
from litedram.frontend.bist import LiteDRAMBISTChecker from litedram.frontend.bist import LiteDRAMBISTChecker
from test.common import DRAMMemory
class TB(Module): class TB(Module):
def __init__(self): def __init__(self):
self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys") self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
@ -13,60 +15,6 @@ class TB(Module):
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port) self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
self.submodules.checker = LiteDRAMBISTChecker(self.read_port) self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
class DRAMMemory:
def __init__(self, width, depth, init=[]):
self.width = width
self.depth = depth
self.mem = []
for d in init:
self.mem.append(d)
for _ in range(depth-len(init)):
self.mem.append(0)
@passive
def read_generator(self, dram_port):
address = 0
pending = 0
while True:
yield dram_port.cmd.ready.eq(0)
yield dram_port.rdata.valid.eq(0)
if pending:
yield dram_port.rdata.valid.eq(1)
yield dram_port.rdata.data.eq(self.mem[address%self.depth])
yield
yield dram_port.rdata.valid.eq(0)
yield dram_port.rdata.data.eq(0)
pending = 0
elif (yield dram_port.cmd.valid):
pending = not (yield dram_port.cmd.we)
address = (yield dram_port.cmd.adr)
yield
yield dram_port.cmd.ready.eq(1)
yield
@passive
def write_generator(self, dram_port):
address = 0
pending = 0
while True:
yield dram_port.cmd.ready.eq(0)
yield dram_port.wdata.ready.eq(0)
if pending:
yield dram_port.wdata.ready.eq(1)
yield
self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
yield dram_port.wdata.ready.eq(0)
yield
pending = 0
elif (yield dram_port.cmd.valid):
pending = yield dram_port.cmd.we
address = (yield dram_port.cmd.adr)
yield
yield dram_port.cmd.ready.eq(1)
yield
def main_generator(dut): def main_generator(dut):
for i in range(100): for i in range(100):
yield yield

53
test/common.py Normal file
View file

@ -0,0 +1,53 @@
from litex.gen import *
class DRAMMemory:
def __init__(self, width, depth, init=[]):
self.width = width
self.depth = depth
self.mem = []
for d in init:
self.mem.append(d)
for _ in range(depth-len(init)):
self.mem.append(0)
@passive
def read_generator(self, dram_port):
address = 0
pending = 0
while True:
yield dram_port.cmd.ready.eq(0)
yield dram_port.rdata.valid.eq(0)
if pending:
yield dram_port.rdata.valid.eq(1)
yield dram_port.rdata.data.eq(self.mem[address%self.depth])
yield
yield dram_port.rdata.valid.eq(0)
yield dram_port.rdata.data.eq(0)
pending = 0
elif (yield dram_port.cmd.valid):
pending = not (yield dram_port.cmd.we)
address = (yield dram_port.cmd.adr)
yield
yield dram_port.cmd.ready.eq(1)
yield
@passive
def write_generator(self, dram_port):
address = 0
pending = 0
while True:
yield dram_port.cmd.ready.eq(0)
yield dram_port.wdata.ready.eq(0)
if pending:
yield dram_port.wdata.ready.eq(1)
yield
self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
yield dram_port.wdata.ready.eq(0)
yield
pending = 0
elif (yield dram_port.cmd.valid):
pending = yield dram_port.cmd.we
address = (yield dram_port.cmd.adr)
yield
yield dram_port.cmd.ready.eq(1)
yield