core/controller: fix burst_length regression introduced by #206.
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@ -45,7 +45,10 @@ class ControllerSettings(Settings):
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class LiteDRAMController(Module):
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class LiteDRAMController(Module):
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def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq,
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def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq,
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controller_settings=ControllerSettings()):
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controller_settings=ControllerSettings()):
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burst_length = phy_settings.nphases * (1 if phy_settings.memtype == "SDR" else 2)
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if phy_settings.memtype == "SDR":
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burst_length = phy_settings.nphases
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else:
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burst_length = burst_lengths[phy_settings.memtype]
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address_align = log2_int(burst_length)
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address_align = log2_int(burst_length)
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# Settings ---------------------------------------------------------------------------------
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# Settings ---------------------------------------------------------------------------------
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