Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

core/controller: fix burst_length regression introduced by #206.

This commit is contained in:
Florent Kermarrec 2020-07-18 23:06:11 +02:00
parent c4ac887ec2
commit f51052f8b7
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litedram/core/controller.py
View File

@ -45,7 +45,10 @@ class ControllerSettings(Settings):
class LiteDRAMController(Module):
def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq,
controller_settings=ControllerSettings()):
burst_length = phy_settings.nphases * (1 if phy_settings.memtype == "SDR" else 2)
if phy_settings.memtype == "SDR":
burst_length = phy_settings.nphases
else:
burst_length = burst_lengths[phy_settings.memtype]
address_align = log2_int(burst_length)
# Settings ---------------------------------------------------------------------------------