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test: clean test_downconverter/test_upconverter (thanks sb0)
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parent
7fbe0b712c
commit
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2 changed files with 14 additions and 20 deletions
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@ -80,14 +80,11 @@ def main_generator(write_port, read_port):
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class TestDownConverter(unittest.TestCase):
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class TestDownConverter(unittest.TestCase):
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def test(self):
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def test(self):
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dut = DUT()
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dut = DUT()
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generators = {
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generators = [
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"sys" : [
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main_generator(dut.write_user_port, dut.read_user_port),
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main_generator(dut.write_user_port, dut.read_user_port),
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read_handler(dut.read_user_port),
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read_handler(dut.read_user_port),
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dut.memory.write_handler(dut.write_crossbar_port),
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dut.memory.write_handler(dut.write_crossbar_port),
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dut.memory.read_handler(dut.read_crossbar_port)
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dut.memory.read_handler(dut.read_crossbar_port)
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]
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]
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}
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run_simulation(dut, generators)
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clocks = {"sys": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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self.assertEqual(write_data, read_data)
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self.assertEqual(write_data, read_data)
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@ -83,14 +83,11 @@ def main_generator(write_port, read_port):
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class TestUpConverter(unittest.TestCase):
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class TestUpConverter(unittest.TestCase):
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def test(self):
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def test(self):
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dut = DUT()
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dut = DUT()
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generators = {
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generators = [
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"sys" : [
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main_generator(dut.write_user_port, dut.read_user_port),
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main_generator(dut.write_user_port, dut.read_user_port),
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read_handler(dut.read_user_port),
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read_handler(dut.read_user_port),
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dut.memory.write_handler(dut.write_crossbar_port),
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dut.memory.write_handler(dut.write_crossbar_port),
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dut.memory.read_handler(dut.read_crossbar_port)
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dut.memory.read_handler(dut.read_crossbar_port)
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]
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]
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}
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run_simulation(dut, generators)
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clocks = {"sys": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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self.assertEqual(write_data, read_data)
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self.assertEqual(write_data, read_data)
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