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2 Commits

Author SHA1 Message Date
Florent Kermarrec 9a50f6ece6 bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6). 2020-11-06 14:44:36 +01:00
Florent Kermarrec 5257197475 bench: add DDR4 Mode Register settings generator. 
Useful to change timing/electrical settings dynamically and bringup/debug DDR4 on new hardware.
 2020-09-24 14:57:14 +02:00