4 Commits

Author	SHA1	Message	Date
Florent Kermarrec	426ae23d2a	examples/litedram_gen: add sdram_module_speedgrade parameter	2018-10-01 11:48:15 +02:00
Florent Kermarrec	30c32f557c	example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)	2018-09-25 10:40:24 +02:00
Florent Kermarrec	cc481be81f	examples: add sdram_rank_nb and user_ports_id_width	2018-09-07 17:55:46 +02:00
Florent Kermarrec	5e4dca9a7b	add examples with standalone cores for arty and genesys2	2018-08-31 23:20:47 +02:00