a3aa4907f1
phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache.
...
(see #255 ).
2021-07-02 09:24:11 +02:00
eb6e7a1514
test/lpddr4: move dfi_data_to_dq to common code
2021-06-22 11:41:44 +02:00
fcda73a175
test/phy_common: simplify calls to run_simulation
2021-06-22 11:41:44 +02:00
da769094fd
phy/lpddr4: fix edge case error with CommandsPipeline ignoring a command
...
Command was being ignored when it occurred on the last phase and
the next command would invalidate the first phase. Now it is fixed
and a regression test is included. A fix in ConstBitSlip has been added
due to wrong Verilog being generated with cycles=1, register=False.
2021-06-22 11:40:51 +02:00
4a96be86c0
test/lpddr4: move run_simulation wrapper to phy_common.py
2021-06-21 14:43:49 +02:00
1543fa4ace
phy/lpddr4: extract common test helpers for use when testing other PHYs
2021-06-21 14:43:49 +02:00
47e8a59511
phy/lpddr4: extract SimulationPads and use it as a base class
2021-06-21 14:43:49 +02:00
8e563239f9
phy/lpddr4: extract common utilities
2021-06-21 13:22:15 +02:00
377d6fac6c
test/test_lpddr4: Disable failing test.
2021-06-08 15:07:53 +02:00
7028944acd
lpddr4: add missing copyright comments
2021-04-01 10:07:02 +02:00
e860d86f3f
lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default)
2021-03-25 15:31:58 +01:00
0ecb1340f5
lpddr4/test: fixes: use 2tCK write preamble, update read latency
2021-03-25 15:31:05 +01:00
5c6796b92a
lpddr4: change MRW command encoding to avoid changing BIOS code
2021-03-25 15:30:48 +01:00
eb1d900c24
lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE
2021-03-25 15:29:17 +01:00
4415a3eaf5
lpddr4: improve simulation and Verilator tests runner
2021-03-25 15:19:16 +01:00
2ab763ac5e
lpddr4: add double-rate PHY, clean up and improve PHY implementation
2021-03-25 15:19:16 +01:00
183f1643aa
lpddr4: add support for MASKED-WRITE
2021-03-25 15:19:16 +01:00
05ed238829
lpddr4: split implementation into multiple files in separate directory
2021-03-25 15:19:16 +01:00
ee9c2b4cf7
lpddr4: implement ZQC through MPC and include it in init sequence
...
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
2021-03-25 15:19:16 +01:00
6943a1a4a5
lpddr4: initial PHY logic and simulation tests
2021-03-25 15:19:08 +01:00
Florent Kermarrec
Jędrzej Boczar