c8423a08a3
test: exit with failure when no benchmarks succeeded
2020-03-12 14:16:21 +01:00
92daf53ea2
test: fix with_uart parameter (see litex/b29f443f)
2020-03-12 14:16:21 +01:00
60b618eeba
Merge pull request #161 from antmicro/jboc/unit-tests
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test: add _LiteDRAMBISTGenerator tests
2020-03-11 16:36:56 +01:00
cdde6bac19
Merge pull request #160 from antmicro/mglb/add-dqs
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common: PHYPadsCombiner: add "dqs" to the list
2020-03-11 16:23:53 +01:00
b89ecdf919
test: add _LiteDRAMBISTGenerator tests
2020-03-11 15:38:13 +01:00
a04b407c81
common: PHYPadsCombiner: add "dqs" to the list
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S6HalfRateDDRPHY uses "dqs" instead of "dqs_p"
2020-03-11 15:01:25 +01:00
6101eab3ac
phy/usddrphy: add assertions on iodelay_clk_freq.
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200MHz min on Ultrascale.
300MHz min on Ultrascale+.
2020-03-10 16:40:44 +01:00
052b436d9a
phy/usddrphy: add USPDDRPHY and rename sim_device parameter to device.
2020-03-10 16:07:53 +01:00
4ec676db27
modules: add MT40A512M8 DDR4.
2020-03-10 13:56:13 +01:00
183f1a6e27
phy/usddrphy: add cdly_value CSR to be able to read back configured clk/cmd delay.
2020-03-10 12:31:19 +01:00
26564ba93c
phys: integrate PHYPadsCombiner.
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pads can now be passed to the PHY as:
# DRAM Chips with common command/address lines (traditional):
pads = platform.request("ddram")
# DRAM Chips with dissociated command/address lines:
pads = [platform.request("ddram", 0), platform.request("ddram", 1)]
LiteDRAM controller will automatically adapts itself to this combined pads.
2020-03-06 18:56:28 +01:00
5e068f412b
common: add PHYPadsCombiner to allow using fully dissociated DRAM chips and combine them to in single DRAM controller.
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Most generally, DRAM chips are sharing command/address lines between chips (using a fly-by
topology since DDR3). On some boards, the DRAM chips are using separate command/address lines
and this combiner can be used to re-create a single pads structure (that will be compatible with
LiteDRAM's PHYs) to create a single DRAM controller from multiple fully dissociated DRAMs chips.
2020-03-06 18:46:07 +01:00
9ad199a116
Merge pull request #158 from antmicro/fix-copyrights
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Fix copyrights
2020-03-05 19:05:33 +01:00
2ce64bd5fb
Fix copyrights
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:40:21 +01:00
8fee3c7edf
test/reference: update kc705 ddr3_init.h.
2020-03-05 11:35:12 +01:00
8122209d9b
modules: add MT40A256M16
2020-02-26 15:48:10 +01:00
a753a3393d
Merge pull request #154 from antmicro/ddr4-sodimm
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modules: add KVR21SE15S8/4 SO-DIMM
2020-02-26 15:16:22 +01:00
3b0ec8f996
modules: add KVR21SE15S8/4 SO-DIMM
2020-02-26 12:59:53 +01:00
752e006cf9
phy/usddrphy: add Ultrascale Plus support.
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Similar to Ultrascale, but SIM_DEVICE needs to be changes to "ULTRASCALE_PLUS".
2020-02-25 10:36:56 +01:00
b8339886da
litedram_gen: add missing ECP5DDRPHY constant
2020-02-22 19:23:28 +01:00
87578dd2e3
Merge pull request #153 from antmicro/jboc/issue-151
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test/benchmarks: add memtype to summary (#151 )
2020-02-20 14:00:27 +01:00
4f9d6e413f
Merge pull request #152 from antmicro/jboc/benchmark
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Benchmarks: add timeout parameter
2020-02-20 14:00:06 +01:00
19cbf7d967
test/benchmarks: add memtype to summary ( #151 )
2020-02-20 13:36:49 +01:00
a5d2c09e8f
test: add benchmark timeout parameter
2020-02-20 09:33:09 +01:00
99e5356369
Merge pull request #150 from antmicro/jboc/latency-sorting
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Benchmarks: fix wrong sorting in benchmarks summary (#149 )
2020-02-20 09:31:19 +01:00
07d2483481
litedram_gen: Limit SDRAM size exposed to the CPU to 16MB.
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This is enough for the Initialization/Calibration and fixes the mapping issues
with large SDRAMs.
2020-02-20 09:29:38 +01:00
53d3a0a9c2
litedram_gen: cleanup ident/align, use dynamic CSRs.
2020-02-20 09:23:32 +01:00
247722d97e
test: fix wrong sorting in benchmarks summary
2020-02-20 09:20:38 +01:00
f1dba787f6
frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid
2020-02-19 18:34:55 +01:00
ebaf612089
Merge pull request #148 from antmicro/jboc/benchmark
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Benchmark: Print heartbeat message during runs in Travis CI
2020-02-19 14:31:33 +01:00
a27841199b
test: option to print heartbeat during benchmarks to avoid Travis timeouts
2020-02-19 13:08:04 +01:00
5fb2b011d8
Merge pull request #146 from antmicro/jboc/benchmark
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Benchmarks: Generate HTML summary and deploy it from Travis
2020-02-18 13:26:20 +01:00
24d33d14d4
Merge pull request #144 from antmicro/sdram-verbosity-benchmark
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test: add option to use sdram timing verifier in benchmarks
2020-02-17 14:55:58 +01:00
878b586c08
Merge pull request #143 from antmicro/addressing-fix
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phy/model: fix memory addressing issues in some configurations
2020-02-17 14:55:24 +01:00
d14254124a
test: run benchmarks in Travis CI and deploy the results
2020-02-17 14:46:50 +01:00
f0be039a34
test: add option to use sdram timing verifier in benchmarks
2020-02-17 14:35:15 +01:00
b7ed91d9f0
test: suppress info log messages in benchmark runner
2020-02-17 13:14:52 +01:00
5719b77ae8
phy: use new BitSlip module with reduced latency (-1 sys_clk cycle)
2020-02-17 12:40:46 +01:00
d646e2a6a7
common: add BitSlip module (with reduced latency)
2020-02-17 12:40:06 +01:00
ef0086e720
phy/model: fix memory addressing issues in some configurations
2020-02-17 12:21:31 +01:00
c6cc0e068d
test: keep benchmark failures in data frame and filter out when needed
2020-02-17 09:07:13 +01:00
bba49f2df8
test: add generation of html benchmarks summary
2020-02-17 09:07:13 +01:00
9083822a74
phy/model: change timing checker parameter, use a verbosity parameter
2020-02-16 16:04:11 +01:00
95b827d435
Merge pull request #142 from antmicro/updated-trefi-verifier
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Update tREFI verifier
2020-02-15 16:32:41 +01:00
0ba31d6d8e
frontend/bist: regroup random_data/random_addr in the same CSRStorage to keep software retro-compatibility
2020-02-15 16:24:59 +01:00
fc27b21a99
frontend/bist: fix LiteDRAMBISTChecker random_data/addr
2020-02-15 16:07:48 +01:00
e0b4278e6f
frontend/bist: set run to 1 by default to keep similar default behaviour than before adding run/ready.
2020-02-15 16:03:45 +01:00
13d0350436
phy/model: add refresh postponing checks
2020-02-14 16:12:22 +01:00
93e220741e
phy/model: check tREFI in 64ms time slices
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This modifies the verifier to by default only check if overall average tREFI length was correct in a 64ms time slice.
Old method that enforces the delay between each REF command is now only used when verbose logging is enabled.
2020-02-14 14:59:34 +01:00
8a46b71411
phy/model: cleanup indent, avoid too long lines.
2020-02-13 17:25:37 +01:00
Jędrzej Boczar
enjoy-digital
Mariusz Glebocki
Karol Gugala
Piotr Binkowski