e0e204a514
litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart).
...
It's more interesting in some design to access the UART through a FIFO like
interface than through RS232.
2021-09-16 17:01:00 +02:00
a11d1b870d
litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY.
...
By specifying FPGA device in .yml files for configs requiring it.
2021-07-02 09:15:42 +02:00
ac825e5112
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
ac33d29727
litedram_gen: simplify and expose bus when CPU is set to None.
2020-05-12 09:07:59 +02:00
fe478382e1
litedram_gen: expose a Bus Slave port instead of a CSR port.
...
The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
2020-05-11 22:47:09 +02:00
e5e4f528d4
examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright
2020-01-27 18:30:24 +01:00
4d19620a37
litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)
2020-01-27 18:20:16 +01:00
340a796129
litedram_gen: add ecp5 support
2020-01-25 18:59:26 +01:00
Florent Kermarrec
Stefan Schrijvers