Alessandro Comodi
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50ba27eb4c
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lpddr5: tests: add additional initial tCK delay for bitslip
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-10-26 12:22:30 +02:00 |
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Alessandro Comodi
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ab130e170a
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lpddr5: add write leveling support
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-10-26 12:22:30 +02:00 |
Jędrzej Boczar
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43aef6255e
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phy/lpddr5: add Verilator tests
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2021-10-26 12:22:30 +02:00 |
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Alessandro Comodi
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abc77f367c
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lpddr5: wck sync: fix syncing and adjusted unit tests
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-10-26 12:22:30 +02:00 |
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Alessandro Comodi
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c4273146c1
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lpddr5: wck sync: adapt tests as now wck sync is required
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-10-26 12:22:30 +02:00 |
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Jędrzej Boczar
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8c10f1405b
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phy/lpddr5: delay WCK sync FSM transition by 1 cycle
With fixed serialization logic WCK sync can be now started later
which avoids the need for special logic when tWCKENL=0.
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2021-10-26 12:22:30 +02:00 |
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Jędrzej Boczar
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32a56ffe28
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phy/lpddr5: fix command serialization
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2021-10-26 12:22:30 +02:00 |
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Jędrzej Boczar
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4e974738d1
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phy/lpddr5: fix column address encoding/decoding
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2021-10-26 12:22:30 +02:00 |
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Jędrzej Boczar
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2671508a11
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phy/lpddr5: add simulation SoC
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2021-10-26 12:22:30 +02:00 |
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Jędrzej Boczar
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7cdf0e11ca
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phy/lpddr5: add unit tests
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2021-10-26 12:22:30 +02:00 |