Florent Kermarrec
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40168db0b4
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test/test_bist: create BISTDriver to simplify test code
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2017-01-17 14:31:24 +01:00 |
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Florent Kermarrec
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c56f90e865
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test/test_bist: simplify and test modules directly not through CSR
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2017-01-17 14:14:50 +01:00 |
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Florent Kermarrec
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ad304c8997
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test: convert to python unittests and some cleanup
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2017-01-17 13:18:11 +01:00 |
Tim 'mithro' Ansell
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c142db3966
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Creating a utility module for easily scoping the LiteDRAMBISTChecker module.
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2016-12-19 17:49:24 +01:00 |
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Florent Kermarrec
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aac61f346e
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test: start fixing bist_tb
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2016-12-17 19:24:12 +01:00 |
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Tim 'mithro' Ansell
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e21b45b608
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Merge remote-tracking branch 'upstream/master' into bist
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2016-12-17 18:15:59 +01:00 |
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Tim 'mithro' Ansell
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bc75d4f3d5
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bist: Reworking as suggested by Florent.
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2016-12-17 17:49:47 +01:00 |
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Tim 'mithro' Ansell
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f1ad8991a4
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bist: Working on improving the names of things.
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2016-12-17 14:09:50 +01:00 |
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Tim 'mithro' Ansell
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8ff2f8779b
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bist: Adding "halt on error" functionality.
Also include ability to see address of error and expected verse actual
data values.
Extend the test bench to test this functionality.
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2016-12-17 14:09:50 +01:00 |
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Tim 'mithro' Ansell
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da144f41d4
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bist: Refactoring test bench.
Move a bunch of common code into common.py
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2016-12-17 14:09:50 +01:00 |
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Tim 'mithro' Ansell
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dc14a98bf4
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bist: s/shoot/start/
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2016-12-17 14:09:50 +01:00 |
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Tim 'mithro' Ansell
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086b905e59
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bist: Improve the basic test bench a little.
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2016-12-17 14:09:50 +01:00 |
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Florent Kermarrec
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ad8ca86e13
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frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly
still some corner cases to manage
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2016-06-15 23:57:16 +02:00 |
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Florent Kermarrec
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5823373243
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frontend: introduce mode on ports: write, read or both
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2016-06-15 17:51:46 +02:00 |
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Florent Kermarrec
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e2b6bda7d0
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test: add random and autocheck on downconverter_tb and upconverter_tb
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2016-06-08 17:33:21 +02:00 |
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Florent Kermarrec
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cb69561137
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phy/model: add we_granularity parameter as simulator bug workaround (to be removed)
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2016-05-28 13:02:40 +02:00 |
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Florent Kermarrec
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8ee2992e5b
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frontend/bist: simplify and use incrementing addressing
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2016-05-26 12:04:41 +02:00 |
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Florent Kermarrec
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2445758eba
|
+x on scripts
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2016-05-26 11:10:03 +02:00 |
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Florent Kermarrec
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b3a11fb669
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frontend: move port adaptation modules to adaptation.py and do adaptation manually (and not in get_port)
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2016-05-26 11:03:55 +02:00 |
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Florent Kermarrec
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3fe3a843e0
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test: also test reads on downconverter/upconverter
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2016-05-24 21:40:46 +02:00 |
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Florent Kermarrec
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32a6e25021
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test: add upconverter_tb and some fixes
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2016-05-24 21:14:49 +02:00 |
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Florent Kermarrec
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de61cefb58
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test: add downconverter_tb and some fixes
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2016-05-24 20:48:26 +02:00 |
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Florent Kermarrec
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6f10314d43
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frontend/bist: remove cd parameter (already available with dram_port.cd)
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2016-05-23 17:37:30 +02:00 |
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Florent Kermarrec
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b258c9a913
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test: add bist_async_tb and some fixes
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2016-05-23 17:20:42 +02:00 |
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Florent Kermarrec
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cb324ea47c
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frontend/bist: LiteDRAMBISTGenerator can now be asynchronous
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2016-05-23 14:17:22 +02:00 |
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Florent Kermarrec
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f36c65b66f
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test: move DRAMMemory model to common
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2016-05-23 13:30:38 +02:00 |
|
Florent Kermarrec
|
94d526a78c
|
test/bist_tb: adapt to new interface
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2016-05-23 13:27:29 +02:00 |
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Florent Kermarrec
|
30bacfeb1b
|
frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests)
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2016-05-13 15:27:12 +02:00 |
|
Florent Kermarrec
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d7458a3c34
|
test: remove common
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2016-05-04 01:16:29 +02:00 |
|
Florent Kermarrec
|
a40b0f760c
|
test/bist_tb: cleanup and add error check
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2016-05-03 22:22:11 +02:00 |
|
Florent Kermarrec
|
836a9d4f00
|
test: removed bank_machine_tb (should be rewritten)
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2016-05-03 19:25:39 +02:00 |
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Florent Kermarrec
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812d7dd7f0
|
frontend/bist: reword bist, add simulation, seems to work but need more testing
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2016-05-03 19:24:33 +02:00 |
|
Florent Kermarrec
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0ef987dab1
|
bankmachine: some changes and first tests
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2015-09-27 23:42:05 +02:00 |
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Florent Kermarrec
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7732ff27a6
|
update code, start bankmachine refactoring and remove old code (will be rewritten)
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2015-09-15 10:22:39 +02:00 |
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Florent Kermarrec
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230bad1b23
|
init structure
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2015-02-22 18:25:36 +01:00 |