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litedram
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https://github.com/enjoy-digital/litedram.git
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0279b770ee
litedram
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bench
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Florent Kermarrec
6fc6174c38
bench/genesys2: expose uart parameter.
2020-09-17 08:22:17 +02:00
..
arty.py
bench: use 115200bauds UART on all targets (fast enough and simplify switch betwen targets).
2020-09-14 10:05:55 +02:00
common.py
bench/common: add s7_load_bios/s7_set_sys_clk functions.
2020-09-14 10:54:35 +02:00
genesys2.py
bench/genesys2: expose uart parameter.
2020-09-17 08:22:17 +02:00
kc705.py
bench: use 115200bauds UART on all targets (fast enough and simplify switch betwen targets).
2020-09-14 10:05:55 +02:00
kcu105.py
bench/kcu105: add a second pll to reduce frequency steps.
2020-08-28 19:03:44 +02:00