Florent Kermarrec 0890908a63 bench/xcu1525: rename ddram_channel arg to channel (since it's a dram specific design).		2020-11-06 10:36:56 +01:00
..
arty.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
common.py	bench/common: add s7_load_bios/s7_set_sys_clk functions.	2020-09-14 10:54:35 +02:00
ddr3_mr_gen.py	bench: add DDR3 Mode Register settings generator.	2020-09-24 17:51:22 +02:00
ddr4_mr_gen.py	bench: add DDR4 Mode Register settings generator.	2020-09-24 14:57:14 +02:00
genesys2.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
kc705.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
kcu105.py	bench/targets: simplify BIST integration using new add_sdram with_bist parameter.	2020-11-06 10:34:26 +01:00
xcu1525.py	bench/xcu1525: rename ddram_channel arg to channel (since it's a dram specific design).	2020-11-06 10:36:56 +01:00