Florent Kermarrec 2113ecfba8 phy/usddrphy: Add missing iteration on pads.clk when multiple ranks.		2021-11-29 08:30:59 +01:00
..
core	core/refresher: Add assert on clk_freq/tREFI ratio.	2021-11-01 14:58:41 +01:00
frontend	frontend/dma/LiteDRAMDMAWriter: Set b.ready to 1 on AXI port.	2021-11-26 11:51:49 +01:00
phy	phy/usddrphy: Add missing iteration on pads.clk when multiple ranks.	2021-11-29 08:30:59 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	Merge pull request #270 from antmicro/jboc/lpddr5-rebase	2021-11-01 22:18:38 +01:00
dfii.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
gen.py	gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz.	2021-11-01 14:28:19 +01:00
init.py	Merge pull request #270 from antmicro/jboc/lpddr5-rebase	2021-11-01 22:18:38 +01:00
modules.py	Merge pull request #283 from antmicro/add-rdimms	2021-11-06 08:30:41 +01:00