Florent Kermarrec 48c17ce8a4 modules: fix tWTR regression on MT46H32M32		2018-10-02 18:53:13 +02:00
..
core	Account for CWL in write to read timing	2018-09-29 12:39:40 -04:00
frontend	test: add test_examples	2018-10-01 11:29:08 +02:00
phy	s6ddrphy: Pass missing nranks parameter.	2018-09-18 16:58:07 -07:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	Merge branch 'master' of https://github.com/enjoy-digital/litedram	2018-10-01 19:36:05 -04:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: fix tWTR regression on MT46H32M32	2018-10-02 18:53:13 +02:00
sdram_init.py	sdram_init: min value for wr is 5	2018-09-05 23:40:04 +02:00