Florent Kermarrec 5257197475 bench: add DDR4 Mode Register settings generator. ... Useful to change timing/electrical settings dynamically and bringup/debug DDR4 on new hardware.		2020-09-24 14:57:14 +02:00
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arty.py	bench: uniformize targets with 125MHz clock and Etherbone.	2020-09-24 13:03:07 +02:00
common.py	bench/common: add s7_load_bios/s7_set_sys_clk functions.	2020-09-14 10:54:35 +02:00
ddr4_mr_gen.py	bench: add DDR4 Mode Register settings generator.	2020-09-24 14:57:14 +02:00
genesys2.py	bench: uniformize targets with 125MHz clock and Etherbone.	2020-09-24 13:03:07 +02:00
kc705.py	bench: uniformize targets with 125MHz clock and Etherbone.	2020-09-24 13:03:07 +02:00
kcu105.py	bench: uniformize targets with 125MHz clock and Etherbone.	2020-09-24 13:03:07 +02:00