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primitives
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test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
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2020-10-02 12:30:19 +02:00 |
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reference
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test/test_init: Update.
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2023-01-10 14:45:27 +01:00 |
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spd_data
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…
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summary
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test: fix wrong sorting in benchmarks summary
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2020-02-20 09:20:38 +01:00 |
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__init__.py
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update code, start bankmachine refactoring and remove old code (will be rewritten)
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2015-09-15 10:22:39 +02:00 |
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access_pattern.csv
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…
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benchmark.py
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global: Switch to litex.gen.genlib.misc.
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2023-07-06 22:06:16 +02:00 |
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benchmarks.yml
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test: update benchmark configuration generator
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2020-02-12 15:42:50 +01:00 |
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common.py
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test/common: fix expected data for test_bist.py
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2023-01-11 17:13:52 +01:00 |
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gen_access_pattern.py
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…
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gen_config.py
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…
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phy_common.py
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phy/utils: DFI rate converter for creating PHY wrappers at slower clocks
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2021-08-04 12:30:56 +02:00 |
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run_benchmarks.py
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…
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test_adaptation.py
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test: check converters at higher data width ratios
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2021-09-01 14:59:05 +02:00 |
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test_adapter.py
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…
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test_avalon.py
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frontend/avalon: properly implement bursts (#340)
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2023-05-31 08:14:52 +02:00 |
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test_axi.py
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axi: Update frontend/test with LiteX changes.
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2022-09-15 17:52:01 +02:00 |
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test_bandwidth.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_bankmachine.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_bist.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_command_chooser.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_crossbar.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_dfi.py
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phy/utils: DFI rate converter for creating PHY wrappers at slower clocks
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2021-08-04 12:30:56 +02:00 |
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test_dma.py
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…
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test_ecc.py
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test/test_ecc: Update.
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2021-06-08 15:07:39 +02:00 |
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test_examples.py
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Make tests safe to run in parallel
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2023-01-11 21:49:50 +01:00 |
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test_fifo.py
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frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width.
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2021-10-06 18:05:48 +02:00 |
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test_init.py
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test/test_init: Update.
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2023-01-10 14:45:27 +01:00 |
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test_lpddr4.py
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Make tests safe to run in parallel
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2023-01-11 21:49:50 +01:00 |
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test_lpddr5.py
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Make tests safe to run in parallel
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2023-01-11 21:49:50 +01:00 |
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test_modules.py
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…
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test_multiplexer.py
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…
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test_phy_utils.py
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test/phy_common: simplify calls to run_simulation
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2021-06-22 11:41:44 +02:00 |
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test_refresh.py
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test/test_refresh: Update.
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2021-11-01 15:33:21 +01:00 |
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test_sim_utils.py
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phy/sim_utils: support low wait times (0/1) in PulseTiming
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2021-10-26 12:22:30 +02:00 |
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test_steerer.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_timing.py
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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test_wishbone.py
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test: check converters at higher data width ratios
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2021-09-01 14:59:05 +02:00 |
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