This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litedram
mirror of
https://github.com/enjoy-digital/litedram.git
Watch
1
Star
0
Fork
You've already forked litedram
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
68c082bf20
litedram
/
bench
History
Florent Kermarrec
5f722a1513
bench/test: Avoid use of ident_version (should fix CI).
2022-02-15 17:33:31 +01:00
..
arty.py
bench/test: Avoid use of ident_version (should fix CI).
2022-02-15 17:33:31 +01:00
common.py
bench/common/bench_test: Improve UART dump speed.
2021-06-29 12:38:44 +02:00
ddr3_mr_gen.py
bench: add DDR3 Mode Register settings generator.
2020-09-24 17:51:22 +02:00
ddr4_mr_gen.py
bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).
2020-11-06 14:44:36 +01:00
genesys2.py
bench/test: Avoid use of ident_version (should fix CI).
2022-02-15 17:33:31 +01:00
kc705.py
bench/test: Avoid use of ident_version (should fix CI).
2022-02-15 17:33:31 +01:00
kcu105.py
bench/test: Avoid use of ident_version (should fix CI).
2022-02-15 17:33:31 +01:00
xcu1525.py
bench/test: Avoid use of ident_version (should fix CI).
2022-02-15 17:33:31 +01:00