litedram/test
2021-11-01 22:18:38 +01:00
..
primitives
reference
spd_data
summary
__init__.py
access_pattern.csv
benchmark.py
benchmarks.yml
common.py test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00
gen_access_pattern.py
gen_config.py
phy_common.py phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
run_benchmarks.py
test_adaptation.py test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00
test_adapter.py
test_axi.py
test_bandwidth.py
test_bankmachine.py
test_bist.py
test_command_chooser.py
test_crossbar.py
test_dfi.py phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
test_dma.py
test_ecc.py
test_examples.py
test_fifo.py frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width. 2021-10-06 18:05:48 +02:00
test_init.py
test_lpddr4.py phy: move regex pattern for parsing SimLogger logs to SimLogger class 2021-10-26 12:22:30 +02:00
test_lpddr5.py lpddr5: tests: add additional initial tCK delay for bitslip 2021-10-26 12:22:30 +02:00
test_modules.py
test_multiplexer.py
test_phy_utils.py
test_refresh.py test/test_refresh: Update. 2021-11-01 15:33:21 +01:00
test_sim_utils.py phy/sim_utils: support low wait times (0/1) in PulseTiming 2021-10-26 12:22:30 +02:00
test_steerer.py
test_timing.py
test_wishbone.py test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00